The embodiments of the present invention relates to a semiconductor device and a method of manufacturing the same.
A dynamic random access memory (DRAM) is one type of semiconductor device and includes a plurality of unit cells constituting of a capacitor and a transistor. The capacitor is used to store data and the transistor is used to transfer data between the capacitor and a bit line in response to a control signal (a word line) using a semiconductor property in which electrical conductivity is changed according to environmental conditions. The transistor includes a gate, a source and a drain. Charges move between the source and drain according to the control signal input to the gate. The charges move between the source and drain through a channel region using properties of the semiconductor.
When the conventional transistor is fabricated on a semiconductor substrate, the gate is formed on the semiconductor substrate and then the source and drain are formed by implanting impurities into the semiconductor substrate, thereby forming the channel region between the source and drain below the gate. The transistor having such a horizontal channel region occupies a large area in the semiconductor substrate. Since a complicated semiconductor memory device includes a plurality of transistors therein, it is difficult to reduce a total area thereof.
When the total area of the semiconductor memory device is reduced, the number of semiconductor memory devices per wafer is increased and productivity can be improved. Various methods of reducing the total area of the semiconductor memory device have been suggested. One of these methods uses a transistor having a recessed gate. In this method a recess is formed in a semiconductor substrate and a channel region is formed along a curvature of the recess instead of a horizontal channel region in the planar gate transistor. Furthermore, a transistor with a buried gate which is formed to be entirely buried within a recess has been studied.
On the other hand, when a semiconductor device having the buried gate is manufactured, a bit line in a cell area and a gate in a peripheral circuit area are simultaneously patterned and thus problems due to performing the same process on the cell area and the peripheral circuit area are caused.
In brief, after the bit line in the cell area and the gate in the peripheral circuit area are simultaneously patterned, an interlayer insulating layer is deposited on the cell area and the peripheral circuit area to define a storage node contact. At this time, boro phosphorous silicate glass (BPSG) is used as the interlayer insulating layer to be precisely buried between the bit lines of the cell area. Here, a spacer which is formed on the gate of the peripheral circuit area is thickly formed to prevent boron of BPSG from penetrating into the semiconductor substrate.
However, the spacer is also thickly formed on a top and sidewall of the bit line in the cell area in addition to in the peripheral circuit area so that a contact area between an active region and a storage node contact in the cell area to be formed in the following is reduced and thus resistance is increased. Further, when the BPSG is formed as the interlayer insulating layer, an annealing process is normally needed and thus operation current of the gate in the peripheral circuit area is reduced and leakage current is increased. When the storage node in the cell area is formed, a hard mask layer as an etch stop layer is thickly formed. This process is similarly adapted in forming a gate so that a height of the gate is increased and it is impossible to easily control a tilt angle in an implantation process.